Contemporary digital circuit test systems often employ a structure named Scan Path. Scan Path is a useful structure that enables testing of a wide variety of digital circuits and systems. In a Scan Path arrangement normally autonomously operated circuit storage elements, such as flip-flips, latches, and other memory capable devices, are reconfigured into a coupled structure - in effect concatenated in series to form a new circuit. Once the normally autonomously operated circuit storage elements are arranged in series a test clock can be used to clock out the states of the memory elements. These clocked-out states can be externally analyzed to determine the correct operation of the digital circuit. Conversely, the test clock can clock in new states and sometime later, after the digital circuit operates on the forced data states, the states of the scan-path arranged storage elements can be readout. This approach is particularly interesting because a large scale system or circuit can be tested with very few additional input-output connections. This is particularly important in integrated circuit design where pins are always expensive.
However, the Scan Path approach has several inherent problems that include primarily complexity and speed of operation. Regarding complexity, each testable concatenatable storage element must be constructed in such a way that it can function as normally expected and also function as a testable element. This requires a significant investment in complexity of the storage element. In order to enable the storage elements to be threaded together, the storage elements structurally are two or three times as complex as simple latches.
Secondarily, the speed of interrogation of the Scan Path is dependent on the size of the concatenated structure. To be circuit complexity efficient these Scan Path structures are relatively large. Also, if only a few storage elements need to be tested the whole Scan Path must be filled or dumped because storage elements are not individually addressable. To increase the throughput of the interrogation prior art schemes have broken the Scan Path structure into more than one Scan Path structure. Although this will increase the testing speed it adversely adds to the circuit's complexity.
What is needed is an improved structure for testing digital circuits that is less complex, and can operate at a higher speed.